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ds100br111 snls338f ? january 2011 ? revised november 2014 ds100br111 ultra low power 10.3 gbps 1-lane repeater with input equalization and output de-emphasis 1 features 3 description the ds100br111 is an extremely low power, high 1 ? two channel repeaters for up to 10.3 gbps performance repeater designed to support serial links ? ds100br210 : 2x unidirectional channels with data rates up to 10.3 gbps. the ds100br111 ? ds100br111 : 1x bidirectional lane pinout is configured as one bidirectional lane (one transmit, one receive channel). the ds100br111 ? 10g-kr bi-directional interface compatibility inputs feature a powerful 4-stage continuous time ? allows for back-channel communication and linear equalizer (ctle) to provide a boost of up to training +36 db at 5 ghz and open an input eye that is ? low 65 mw/channel (typical) power completely closed due to inter-symbol interference consumption, with option to power down unused (isi) induced by the interconnect mediums such as board traces or twin-axial copper cables. the channels transmitter features a programmable output de- ? advanced signal conditioning features emphasis driver with up to -12 db and can drive ? receive equalization up to +36 db output voltage levels from 700 mvp-p to 1300 mvp-p. ? transmit de-emphasis up to -12 db when configured as a 10g-kr repeater, the ? transmit vod control: 700 to 1300 mvp-p ds100br111 allows the kr host and the end point to optimize the full link by adjusting transmit and receive ? low residual dj at 10.3 gbps equalizer coefficients using back-channel ? programmable via pin selection, eeprom, or communication techniques specified by the 802.3ap smbus interface ethernet standard. ? single supply voltage: 2.5 v or 3.3 v the programmable settings can be applied via pin ? flow-thru pinout in 4 mm 4 mm 24-pin leadless control, smbus protocol, or an external eeprom. in wqfn package the eeprom mode, the configuration information is ? 5 kv hbm esd rating automatically loaded on power up, thereby eliminating the need for an external microprocessor or software ? -40 to 85 c operating temperature range driver. 2 applications device information (1) ? high-speed active copper cable modules and part number package body size (nom) fr-4 backplane in communication systems ds100br111 wqfn (24) 4.00 mm x 4.00 mm ? 10ge, 10g-kr, fc, sas, sata 3/6 gbps (with (1) for all available packages, see the orderable addendum at oob detection), infiniband, cpri, rxaui and the end of the datasheet. many others 4 simplified schematic typical application 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. in+ in- eq idle detect outbuf smbus vod/ de-emphasis control vdd smbus tx idle enable dem eq[1:0] out+ out- 50 : 50 : vod smbus los channel status and control sd_th tx_dis mode line card ds100br111 1x10g asic fpga 1x10g 1 x sfp+ productfolder sample &buy technical documents tools & software support &community
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com table of contents 8.3 feature description ................................................. 13 1 features .................................................................. 1 8.4 device functional modes ........................................ 13 2 applications ........................................................... 1 8.5 programming ........................................................... 16 3 description ............................................................. 1 8.6 register maps ......................................................... 30 4 simplified schematic ............................................. 1 9 application and implementation ........................ 37 5 revision history ..................................................... 2 9.1 application information ............................................ 37 6 pin configuration and functions ......................... 3 9.2 typical application ................................................. 38 7 specifications ......................................................... 6 10 power supply recommendations ..................... 45 7.1 absolute maximum ratings ...................................... 6 10.1 power supply bypass ........................................... 46 7.2 handling ratings ....................................................... 6 11 layout ................................................................... 46 7.3 recommended operating conditions ....................... 6 11.1 layout guidelines ................................................. 46 7.4 electrical characteristics ........................................... 6 11.2 layout example .................................................... 47 7.5 electrical characteristics ? serial management bus 12 device and documentation support ................. 48 interface .................................................................... 9 12.1 documentation support ........................................ 48 7.6 timing requirements ? los and enable / disable timing ........................................................ 9 12.2 trademarks ........................................................... 48 7.7 typical characteristics ............................................ 11 12.3 electrostatic discharge caution ............................ 48 8 detailed description ............................................ 12 12.4 glossary ................................................................ 48 8.1 overview ................................................................. 12 13 mechanical, packaging, and orderable 8.2 functional block diagram ....................................... 12 information ........................................................... 48 5 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision e (february 2013) to revision f page ? added, updated, or renamed the following sections: device information table, application and implementation ; power supply recommendations ; layout ; device and documentation support ; mechanical, packaging, and ordering information .............................................................................................................................................................. 1 2 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 6 pin configuration and functions 24-pin rtw package top view (1) the center dap on the package bottom is the device gnd connection. this pad must be connected to gnd through multiple (minimum of 4) vias to ensure optimal electrical and thermal performance. pin functions (1) pin i/o, type description name number differential high speed i/o's inverting and non-inverting cml differential inputs to the equalizer. on-chip 50 ina+, ina- , 24, 23 i, cml termination resistors connect both inx+ and inx- to vdd. compatible with ac coupled inb+, inb- 11, 12 cml inputs. outa+, outa-, 7, 8 inverting and non-inverting 50 driver outputs with de-emphasis. compatible with ac o, cml outb+, outb- 20, 19 coupled cml inputs. control pins system management bus (smbus) enable pin i, 4-level, high = register access smbus slave mode ensmb 3 lvcmos float = read external eeprom (smbus master mode) tie 1 k to gnd = pin mode (1) lvcmos inputs without the ? float ? conditions must be driven to a logic low or high at all times or operation is not ensured. unless the " float " level is desired, 4-level input pins require a minimum 1 k resistor to gnd, vdd (in 2.5 v mode), or vin (in 3.3 v mode). input edge rate for lvcmos/float inputs must be faster than 50 ns from 10 ? 90%. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: ds100br111 ina+ ina- outb+ vdd_sel vin 18 inb+ inb- 17 14 13 16 los _______ vod_sel / readen _____ mode / done sd_th outa+ outa- outb- smbus and control 15 vdd 24 23 22 21 20 19 11 12 8 10 9 7 eqb1/ad2 ensmb 1 2 5 63 scl/demb eqb0/ad3 sda/dema 4 vdd tx_dis ad1/eqa1 ad0/eqa0
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com pin functions (1) (continued) pin i/o, type description name number ensmb = float or 1 (smbus modes) i, 2-level, clock output when loading eeprom configuration, reverting to smbus clock input lvcmos, when eeprom load is complete ( all_done = 0). scl 5 o, open external 2 k to 5 k pull-up resistor to vdd (2.5 v mode) or vin (3.3 v mode) drain recommended as per smbus interface standards (2) i, 2-level, in both smbus modes, this pin is the smbus data i/o. data input or open drain output. lvcmos, external 2 k to 5 k pull-up resistor to vdd (2.5 v mode) or vin (3.3 v mode) sda 4 o, open recommended as per smbus interface standards (2) drain ensmb master or slave mode i, 4-level, smbus slave address inputs. in smbus mode, these pins are the user set smbus ad0-ad3 10, 9, 2, 1 lvcmos slave address inputs. there are 16 addresses supported by these pins. pins must be tied low or high when used to define the device smbus address. (3) ensmb = float: when using smbus master mode, a logic low on this pin starts the load from the external eeprom. i, 2-level, readen 17 ensmb = 1: when using smbus slave mode, the vod_sel/ readen pin must be lvcmos tied low for the ad[3:0] to be active. if this pin is tied high or left floating, an address of 0xb0 will be used for the ds100br111. when using an external eeprom (ensmb = float), valid register load status o, 2-level, output done 18 lvcmos high = external eeprom load failed or incomplete low = external eeprom load passed ensmb = 0 (pin mode) eqa[1:0] and eqb[1:0] control the level of equalization on the input pins. eqa[1:0] controls the a channel, and eqb[1:0] controls the b channel. the pins are only active eqa0, eqa1 10, 9 i, 4-level, when ensmb = 0. eqb0, eqb1 1, 2 lvcmos when ensmb = 1, the smbus registers provide independent control of each channel, and the eqb0/b1 pins are converted to smbus ad2/ad3 inputs. see table 3 for additional information. dema and demb control the level of de-emphasis for the output driver when in 10g mode. dema controls the a channel, and demb controls the b channel. the pins are i, 4-level, only active when ensmb = 0. dema, demb 4, 5 lvcmos when ensmb = 1, the smbus registers provide independent control of each channel, and the dem pins are converted to smbus scl and sda pins. see table 4 for additional information. vod select high = 10g-kr mode (vod = 1.1 vpp or 1.3 vpp) i, 4-level, float = (vod = 1.0 vpp) vod_sel 17 lvcmos 20 k to gnd = (vod = 1.2 vpp) 1 k to gnd = (vod = 700 mvpp) see (3) (4) for additional notes. see table 2 for additional information. controls device mode of operation high= 10gbe mode, continuous talk (output always on) i, 4-level, float = 10g-kr mode, slow oob mode 18 lvcmos 20 k to gnd = esata mode, fast oob, auto low power on 100 s of inactivity. sd stays active. 1 k to gnd = sas mode, fast oob (2) scl and sda pins can be tied either to 3.3 v or 2.5 v, regardless of whether the device is operating in 2.5 v mode or 3.3 v mode. (3) setting vod_sel = high in smbus mode will force the smbus address = 0xb0 (4) ds100br111 outa is limited to 700 mvpp in pin mode. 4 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 pin functions (1) (continued) pin i/o, type description name number control pins ? both pin and smbus modes (lvcmos) i, 2-level, high = outa enabled, outb disabled tx_dis 6 lvcmos low = outa and outb enabled o, open indicates loss of signal (default is los on ina). can be modified via smbus los 13 drain registers. the sd_th pin controls los threshold setting assert (mvpp), deassert (mvpp) i, 4-level, high = 190 mvpp, 130 mvpp sd_th 14 lvcmos float = 180 mvpp, 110 mvpp (default) 20 k to gnd = 160 mvpp, 100 mvpp 1 k to gnd = 210 mvpp, 150 mvpp (5) enables the 3.3 v to 2.5 v internal regulator vdd_sel 16 i, float low = 3.3 v operation float = 2.5 v operation power power supply pins when in 2.5 v mode, connect to 2.5 v supply. vdd 21, 22 power when in 3.3 v mode, do not connect to any supply voltage. should be used to attach external decoupling to device, 100 nf recommended. see power supply recommendations for additional information. vin = 3.3 v 10% (input to internal ldo regulator) vin 15 power when in 2.5 v mode, vin pin must be left floating. see power supply recommendations for additional information. gnd dap power ground pad (dap - die attach pad). (5) using values less than the default level can extend the time required to detect los and are not recommended. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com 7 specifications 7.1 absolute maximum ratings (1) (2) min max unit supply voltage (vdd) -0.5 +2.75 v supply voltage (vin) -0.5 +4.0 v lvcmos input/output voltage -0.5 +4.0 v cml input voltage -0.5 (vdd+0.5) v cml input current -30 +30 ma junction temperature 125 c (1) ? absolute maximum ratings ? indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. functional operation of the device and/or non-degradation at the absolute maximum ratings or other conditions beyond those indicated in the recommended operating conditions is not implied. (2) for soldering specifications, see snoa549 . 7.2 handling ratings min max unit t stg storage temperature range -40 +125 c human body model (hbm), per ansi/esda/jedec js-001, all -5 5 kv pins (1) v (esd) electrostatic discharge machine model (mm), std - jesd22-a115-a 100 v charged device model (cdm), per jedec specification 1250 v jesd22-c101, all pins (2) (1) jedec document jep155 states that 500 v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250 v cdm allows safe manufacturing with a standard esd control process. 7.3 recommended operating conditions (1) min typ max unit supply voltage (2.5 v mode) 2.375 2.5 2.625 v supply voltage (3.3 v mode) 3.0 3.3 3.6 v ambient temperature -40 25 +85 c smbus (sda, scl) 3.6 v (1) the recommended operating conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. absolute maximum numbers are ensured for a junction temperature range of -40 c to +125 c. models are validated to maximum operating voltages only. 7.4 electrical characteristics parameter test conditions min typ max unit power supply current tx_dis = low, eq = on 50 63 vod_sel = float (1000 mvpp) auto low power mode idd supply current tx_dis = low, mode = 20 k ma 12 15 vid cha and chb = 0.0 v vod_sel = float (1000 mvpp) tx_dis = high 25 35 lvcmos dc specifications high level input voltage, v ih25 2.5 v supply mode 2.0 vdd v 2-level lvcmos high level input voltage, v ih33 3.3 v supply mode 2.0 vin v 2-level lvcmos low level input voltage, v il gnd 0.7 v 2-level lvcmos 6 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 electrical characteristics (continued) parameter test conditions min typ max unit v oh high level output voltage i oh = -4.0 ma (1) 2.0 v v ol low level output voltage i ol = 4.0 ma 0.4 v vinput = 0 v or vdd -15 +15 vdd_sel = float i in input leakage current a vinput = 0 v or vin -15 +15 vdd_sel = low vinput = 0 v or vdd - 0.05 v input leakage current vdd_sel = float i in-p -160 +80 a 4-level input (2) vinput = 0 v or vin - 0.05 v vdd_sel = low cml receiver inputs source transmit launch default power-up conditions v tx 190 800 1600 mvp-p differential signal level ensmb = 0 or 1 sdd11 @ 4.1 ghz -12 rl rx-in rx return loss sdd11 @ 11.1 ghz -8 db scd11 @ 11.1 ghz -10 high speed transmitter outputs out+ and out- ac coupled and terminated by 50 to gnd v od1 output voltage differential swing 500 650 800 vod_sel = low (700 mvpp setting) de = low out+ and out- ac coupled and terminated by 50 to gnd v od2 output voltage differential swing 800 1000 1100 vod_sel = float (1000 mvpp setting) mvp-p de = low out+ and out- ac coupled and terminated by 50 to gnd v od3 output voltage differential swing vod_sel = 20 k to gnd (1200 950 1150 1350 mvpp) de = low out+ and out- ac coupled and terminated by 50 to gnd v od_de1 de-emphasis levels -3 db vod_sel = float (1000 mvpp) de = float out+ and out- ac coupled and terminated by 50 to gnd v od_de2 de-emphasis levels -6 db vod_sel = float (1000 mvpp) de = 20 k to gnd (1) voh only applies to the done pin; los, scl, and s da are open-drain outputs that have no internal pull-up capability. done is a full lvcmos output with pull-up and pull-down capability. (2) input is held to a maximum of 50 mv below vdd or vin to simulate the use of a 1 k resistor on the input. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com electrical characteristics (continued) parameter test conditions min typ max unit out+ and out- ac coupled and terminated by 50 to gnd v od_de3 de-emphasis levels -9 db vod_sel = float (1000 mvpp) de = high ac common mode voltage v cm-ac output common-mode voltage 4.5 mv (rms) de = 0 db, vod 1000 mvpp output dc common-mode dc common mode voltage v cm-dc 0 1.1 1.9 v voltage v idle tx idle output voltage vid = 0 mvp-p 30 mv sdd22 @ 4.1 ghz -13 sdd22 @ 11.1 ghz -9 rl tx-diff tx return loss db scc22 @ 2.5 ghz -22 scc22 @ 11.1 ghz -10 transmitter termination dc, i force = 100 a (3) delta_z m 2.5% mismatch t r/f transmitter rise and fall time measurement points at 20% - 80% (4) 38 ps measured at 50% crossing t pd propagation delay 230 ps eq = 0x00 t ccsk channel to channel skew t = 25 c, vdd = 2.5 v 7 ps t ppsk part to part skew t = 25 c, vdd = 2.5 v 20 ps t tx-idle-set-to- max time to transition to idle after vin = 1 vpp, 10 gbps 6.5 ns idle differential signal eq = 0x00, de = 0 db t tx-idle-to- max time to transition to valid vin = 1 vpp, 10 gbps 3.2 ns diff-data differential signal after idle eq = 0x00, de = 0 db active oob timing distortion, t env_distort input active time vs. output active 3.3 ns time output jitter specifications (5) r j random jitter no media 0.3 ps (rms) source amplitude = 700 mvpp, prbs15 pattern, 10.3125 gbps d j1 deterministic jitter 0.09 ui vod = default, eq = minimum, de = 0 db equalization 10.3125 gbps 8 meter 30awg cable on input d je1 residual deterministic jitter 0.27 ui source = 700 mvpp, prbs15 pattern eq = 0x0f 10.3125 gbps 30 " 4-mil fr4 on inputs d je2 residual deterministic jitter 0.17 ui source = 700 mvpp, prbs15 pattern eq = 0x16 de-emphasis 10.3125 gbps 10 ? 4 mil stripline fr4 on outputs d jd1 residual deterministic jitter source = 700 mvpp, prbs15 pattern 0.13 ui eq = min, vod = 1200 mvpp, de = -3.5 db (3) force 100 a on output, measure v on the output and calculate impedance. mismatch is the percentage difference of outn+ and outn- impedance driving the same logic state. (4) default vod used for testing. de = -1.5 db level used to compensate for fixture attenuation. (5) typical jitter reported is determined by jitter decomposition software on the dsa8200 oscilloscope. 8 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 7.5 electrical characteristics ? serial management bus interface over recommended operating supply and temperature ranges unless other specified. parameter test conditions min typ max unit serial bus interface dc specifications (1) v il data, clock input low voltage 0.8 v v ih data, clock input high voltage 2.1 3.6 v i pullup current through pull-up resistor high power specification 4 ma or current source v dd nominal bus voltage 2.375 3.6 v i leak-bus input leakage per bus segment see (2) -200 +200 a c i capacitance for sda and scl see (2) (3) (4) 10 pf r term external termination resistance pullup v dd = 3.3 v, see (2) (3) (5) 2000 ? pull to v dd = 2.5v 5% or 3.3v pullup v dd = 2.5 v, see (2) (3) (5) 1000 ? 10% serial bus interface timing specifications ensmb = vdd (slave mode) 400 khz fsmb bus operating frequency ensmb = float (master mode) (1) 280 400 520 khz bus free time between stop and t buf 1.3 s start condition t hd:sta hold time after (repeated) start at i pullup , max condition. after this period, the 0.6 s first clock is generated. t su:sta repeated start condition setup 0.6 s time t su:sto stop condition setup time 0.6 s t hd:dat data hold time 0 ns t su:dat data setup time 100 ns t low clock low period 1.3 s t high clock high period see (6) 0.6 50 s t f clock/data fall time see (6) 300 ns t r clock/data rise time see (6) 300 ns time in which a device must be t por see (4) (6) 500 ms operational after power-on reset (1) eeprom interface requires 1 mhz capable eeprom device. (2) recommended value. (3) recommended maximum capacitance load per bus segment is 400 pf. (4) ensured by design and characterization. parameter not tested in production. (5) maximum termination voltage should be identical to the device supply voltage. (6) compliant to smbus 2.0 physical layer specification. see system management bus (smbus) specification version 2.0, section 3.1.1 smbus common ac specifications for details. 7.6 timing requirements ? los and enable / disable timing parameter test conditions min typ max unit input idle to active t los_off see (1) 0.035 s rx_los response time input active to idle t los_on see (1) 0.4 s rx_los response time tx disable assert time t off see (1) 0.005 s tx_dis = high to output off tx disable negatetime t on see (1) 0.150 s tx_dis = low to output on auto low power exit t lp_exit see (1) 150 ns alp to normal operation auto low power enter t lp_enter see (1) 100 s normal operation to auto low power (1) parameter not tested in production. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com figure 1. output rise and fall transition times figure 2. propagation delay timing diagram figure 3. transmit idle-data and data-idle response time figure 4. smbus timing parameters 10 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111 in 0v t plhd out 0v t phld 0v 20% 80% 20% 80% t fall t rise vod = [out+ - out-] sp t buf t hd:sta t low t r t hd:dat t high t f t su:dat t su:sta st sp t su:sto scl sda st in out + - t idle-data + - t data-idle data idle 0v 0v data idle
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 7.7 typical characteristics the following data was collected at 25 c. vod = 700 mvpp figure 5. supply current vs. output voltage setting figure 6. supply current vs. supply voltage figure 7. output voltage vs. output voltage setting copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: ds100br111 0 1 2 3 4 5 6 7 500 600 700 800 900 1000 1100 1200 1300 1400 1500 output voltage (mvpp) vod level 700 800 900 1000 1100 1200 1300 0 10 20 30 40 50 60 70 80 90 100 supply current (ma) output voltage (mvpp) 3.3v mode 2.5v mode 2.0 2.2 2.4 2.6 2.8 3.0 40 44 48 52 56 60 supply current (ma) supply voltage (v) 2.5v mode
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com 8 detailed description 8.1 overview the ds100br111 is a high performance bidirectional 1-lane repeater optimized for 10g-kr and sas/sata operation, where its programmable equalization and de-emphasis compensate for lossy fr-4 printed circuit board backplanes or balanced cables. the ds100br111 operates in 3 modes: pin control mode (ensmb = 0), smbus slave mode (ensmb = 1), and smbus master mode (ensmb = float) to load register information from external eeprom. each channel has a signal detector circuit that monitors the input signal amplitude. when the input signal level is below the detector's de-assert level, the output is disabled. when input signal level exceeds the detector's assert level, the output is enabled. the signal detector circuit is used to support the oob signaling used in sas and sata. 8.2 functional block diagram 12 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111 ina+ ina- eq outa+ outa- a channel term pre- driver driver eqa[1:0] ensmb dema digital core and smbus registers scl sda tx_dis vin vdd_sel ad[3:0] internal voltage regulator readen done vod_sel inb+ inb- eq outb+ outb- term pre- driver driver eqb[1:0] ensmb demb vod_sel b channel signal detect signal detect note: this diagram is representative of device signal flow onl y.
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 8.3 feature description 8.3.1 4-level control pin settings the 4-level input pins use a resistor divider to set the four valid control levels and provide a wider range of control settings when ensmb = 0. there is an internal 30-k pull-up and a 60-k pull-down connected to the package pin. these resistors, together with the external resistor connection, combine to achieve the desired voltage level. by using the 1-k pull-down, 20-k pull-down, no connect, or 1-k pull-up, the optimal voltage levels for each of the four input states are achieved as shown in table 1 . table 1. 4 ? level control pin settings table resulting pin voltage level setting 3.3 v mode 2.5 v mode 0 tie 1 k to gnd 0.10 v 0.08 v r tie 20 k to gnd 1/3 x v in 1/3 x v dd f float (leave pin open) 2/3 x v in 2/3 x v dd 1 tie 1 k to v in or v dd v in - 0.05 v v dd - 0.04 v typical 4-level input thresholds : ? internal threshold between 0 and r = 0.2 * v in or v dd ? internal threshold between r and f = 0.5 * v in or v dd ? internal threshold between f and 1 = 0.8 * v in or v dd in order to minimize the startup current associated with the integrated 2.5-v regulator, the 1-k pull-up / pull- down resistors are recommended. if several four level inputs require the same setting, it is possible to combine two or more 1-k resistors into a single lower value resistor. as an example, combining two inputs with a single 500- resistor is a valid way to save board space. 8.4 device functional modes 8.4.1 pin control mode when in pin mode (ensmb = 0), equalization, de-emphasis, and vod (output amplitude) can be selected via external pin control for both the a-channel and b-channel. equalization and de-emphasis can be programmed by pin selection for each side independently. for further device control, the vod_sel and mode pins are available to improve ds100br111 performance depending on design applications. the receiver electrical idle detect threshold is also adjustable via the sd_th pin. pin control mode is ideal in situations where neither mcu or eeprom is available to access the device via smbus sda and scl lines. 8.4.2 smbus slave mode when in slave smbus mode (ensmb = 1), equalization, de-emphasis, and vod (output amplitude) are all programmable on an individual channel basis. upon assertion of ensmb, the eqx, demx, and vodx settings are controlled by smbus immediately. it is important to note that smbus settings can only be changed from their defaults after asserting register enable by setting reg 0x06[3] = 1. the eqx, demx, and vodx pins are subsequently converted to ad0-ad3 smbus address inputs. the other external control pins (tx_dis, mode, and sd_th) remain active unless their respective registers are written to and the appropriate override bit is set. if the user overrides a pin control, the input voltage level of that control pin is ignored until ensmb is driven low (pin mode). in the event that channels are powered down via the tx_dis pin, register setting states are not affected. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com device functional modes (continued) table 2. signal detect threshold level (1) smbus reg bit typical assert level typical de-assert level level sd_th (pin 14) [3:2] and [1:0] (mvpp) (mvpp) 1 0 10 210 150 2 r 01 160 100 3 f (default) 00 180 110 4 1 11 190 130 (1) typical assert and de-assert levels were measured with vdd = 2.5 v, 25 c, and 010101 pattern at 8 gbps. 8.4.3 smbus master mode when in smbus master mode (ensmb = float), the equalization, de-emphasis, and vod (output amplitude) for multiple devices can be loaded via external eeprom. by asserting a float condition on the ensmb pin, an external eeprom writes register settings to each device in accordance with its smbus slave address. the settings programmable by external eeprom provide only a subset of all the register bits available via smbus slave mode, and the bit-mapping between smbus slave mode registers and eeprom addresses can be referenced in table 6 . once the eeprom successfully finishes loading each device's register settings, the device reverts back to smbus slave mode and releases sda and scl control to an external master mcu. if the eeprom fails to load settings to a particular device, for example due to an invalid or blank hex file, the device waits indefinitely in an unknown state where access to the smbus lines is not possible. 8.4.4 signal conditioning settings equalization, de-emphasis, and vod settings accessible via the pin controls are chosen to meet the needs of most high speed applications. for additional levels and flexibility in eq, de-emphasis, and vod programming, these settings can be controlled via the smbus registers. each control pin input has a total of four possible voltage level settings. in pin mode, table 3 shows the 16 eq settings available, and table 4 shows the 16 de- emphasis and vod combination settings available. note that when in pin mode, only 16 of a possible 256 eq programmable levels can be accessed by setting the eqx[1:0] pins. in addition, each pin setting applied to the vod_sel and demx pin input programs a fixed combination of vod and de-emphasis. in order to access all 256 eq levels and control both vod and de-emphasis settings independently, smbus register access must be used. table 3. equalizer settings equalization boost relative to dc eqa1 eqa0 level eq ? 8 bits [7:0] db boost at 5 ghz suggested media (1) eqb1 eqb0 1 0 0 0000 0000 = 0x00 2.5 fr4 < 5 inch trace 2 0 r 0000 0001 = 0x01 6.5 fr4 5 inch trace 3 0 f 0000 0010 = 0x02 9 fr4 10 inch trace 4 0 1 0000 0011 = 0x03 11.5 fr4 15 inch trace 5 r 0 0000 0111 = 0x07 14 fr4 20 inch trace 6 r r 0001 0101 = 0x15 15 fr4 25 inch trace 7 r f 0000 1011 = 0x0b 17 fr4 25 inch trace 8 r 1 0000 1111 = 0x0f 19 7m 30 awg cable 9 f 0 0101 0101 = 0x55 20 fr4 30 inch trace (1) settings are approximate and will change based on pcb material, trace dimensions, and driver waveform characteristics. optimal eq settings should be determined via simulation and prototype verification. 14 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 table 3. equalizer settings (continued) equalization boost relative to dc eqa1 eqa0 level eq ? 8 bits [7:0] db boost at 5 ghz suggested media (1) eqb1 eqb0 8m 30 awg cable 10 f r 0001 1111 = 0x1f 23 fr4 35 inch trace 11 f f 0010 1111 = 0x2f 25 10m 30 awg cable 12 f 1 0011 1111 = 0x3f 27 13 1 0 1010 1010 = 0xaa 30 14 1 r 0111 1111 = 0x7f 31 10m to 12m, cable 15 1 f 1011 1111 = 0xbf 33 16 1 1 1111 1111 = 0xff 34 table 4. de-emphasis and output voltage settings (1) smbus register smbus register level vod_sel (2) (3) dema/b vod (mvpp) dem (db) dem level vod level 1 0 0 000 000 700 0 2 0 f 010 000 700 -3.5 3 0 r 011 000 700 -6 4 0 1 101 000 700 -9 5 f 0 000 011 1000 0 6 f f 010 011 1000 -3.5 7 f r 011 011 1000 -6 8 f 1 101 011 1000 -9 9 r 0 000 101 1200 -0 10 r f 010 101 1200 -3.5 11 r r 011 101 1200 -6 12 r 1 101 101 1200 -9 13 1 0 000 100 1100 0 14 1 f 001 100 1100 -1.5 15 1 r 001 110 1300 -1.5 16 1 1 010 110 1300 -3.5 (1) the ds100br111 vod for output a is limited to 700 mvpp in pin mode (ensmb=0). with ensmb = 1 or float, the vod for output a can be adjusted with smbus register 0x23 [4:2] as shown in table 9 . (2) when vod_sel is in the logic 1 state (1 k resistor to vin or vdd), the ds100br111 will support 10g-kr back-channel communication using pin control. (3) in smbus mode, if vod_sel is in the logic 1 state (1 k resistor to vin or vdd), the ds100br111 ad0-ad3 pins are internally forced to 0. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com 8.5 programming 8.5.1 system management bus (smbus) and configuration registers the system management bus interface is compatible with the smbus 2.0 physical layer specification. tie ensmb = 1 k to vdd (2.5 v mode) or vin (3.3 v mode) to enable smbus slave mode and allow access to the configuration registers. the ds100br111 uses ad[3:0] inputs in both smbus modes. these ad[3:0] pins are the user set smbus slave address inputs and have internal pull-downs. based on the smbus 2.0 specification, the ds100br111 has a 7- bit slave address. the lsb is set to 0'b (for a write). when ad[3:0] pins are left floating or pulled low, ad[3:0] = 0000'b, and the device default address byte is 0xb0. the device supports up to 16 address bytes, as shown in table 5 . table 5. device slave address bytes full slave address byte ad[3:0] settings 7-bit slave address (hex) (7-bit address + write bit) 0000 b0 58 0001 b2 59 0010 b4 5a 0011 b6 5b 0100 b8 5c 0101 ba 5d 0110 bc 5e 0111 be 5f 1000 c0 60 1001 c2 61 1010 c4 62 1011 c6 63 1100 c8 64 1101 ca 65 1110 cc 66 1111 ce 67 the sda and scl pins are 3.3 v tolerant, but are not 5 v tolerant. an external pull-up resistor is required on the sda and scl line. the resistor value can be from 2 k to 5 k depending on the voltage, loading, and speed. 16 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 8.5.2 transfer of data via the smbus during normal operation, the data on sda must be stable during the time when scl is high. there are three unique states for the smbus: ? start: a high-to-low transition on sda while scl is high indicates a message start condition. ? stop: a low-to-high transition on sda while scl is high indicates a message stop condition. ? idle: if scl and sda are both high for a time exceeding t buf from the last detected stop condition or if they are high for a total exceeding the maximum specification for t high , then the bus will transfer to the idle state. 8.5.3 smbus transactions the device supports write and read transactions. see table 9 for register address, type (read/write, read only), default value, and function information. 8.5.4 writing a register to write a register, the following protocol is used (see smbus 2.0 specification): 1. the host drives a start condition, the 7-bit smbus address, and a ? 0 ? indicating a write. 2. the device (slave) drives the ack bit ( ? 0 ? ). 3. the host drives the 8-bit register address. 4. the device drives an ack bit ( ? 0 ? ). 5. the host drive the 8-bit data byte. 6. the device drives an ack bit ( ? 0 ? ). 7. the host drives a stop condition. once the write transaction is completed, the bus goes idle and communication with other smbus devices may now occur. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com 8.5.5 reading a register to read a register, the following protocol is used (see smbus 2.0 specification): 1. the host drives a start condition, the 7-bit smbus address, and a ? 0 ? indicating a write. 2. the device (slave) drives the ack bit ( ? 0 ? ). 3. the host drives the 8-bit register address. 4. the device drives an ack bit ( ? 0 ? ). 5. the host drives a start condition. 6. the host drives the 7-bit smbus address, and a ? 1 ? indicating a read. 7. the device drives an ack bit ? 0 ? . 8. the device drives the 8-bit data value (register contents). 9. the host drives a nack bit ? 1 ? indicating end of the read transfer. 10. the host drives a stop condition. once the read transaction is completed, the bus goes idle and communication with other smbus devices may now occur. please see table 9 for more information. 8.5.6 eeprom programming the ds100br111 supports reading directly from an external eeprom device by implementing smbus master mode. when used in smbus master mode, the ds100br111 will read directly from a specific location in the external eeprom. when designing a system that uses external eeprom, the following guidelines should be followed: ? set the ds100br111 in smbus master mode. ? ensmb (pin 3) = float ? the external eeprom device must support 1 mhz operation. ? the external eeprom device address byte must be 0xa0. ? set the ad[3:0] inputs for smbus address byte. when ad[3:0] = 0000'b, the device address byte is 0xb0. ? the device address can be set with the use of the ad[3:0] input up to 16 different addresses. use the example below to set each of the smbus addresses. ? ad[3:0] = 0001'b, the device address byte is 0xb2 ? ad[3:0] = 0010'b, the device address byte is 0xb4 ? ad[3:0] = 0011'b, the device address byte is 0xb6 ? ad[3:0] = 0100'b, the device address byte is 0xb8 ? the master implementation in the ds100br111 supports multiple devices reading from one eeprom. when tying multiple devices to the sda and scl pins, use these guidelines: ? use adjacent smbus addresses for the 4 devices ? use a pull-up resistor on sda; value = 4.7 k ? ? use a pull-up resistor on scl: value = 4.7 k ? ? daisy-chain readen (pin 17) and done (pin 18) from one device to the next device in the sequence. 1. tie readen of the 1st device in the chain (u1) to gnd 2. tie done of u1 to readen of u2 3. tie done of u2 to readen of u3 4. tie done of u3 to readen of u4 5. optional: tie done of u4 to a led to show each of the devices have been loaded successfully 18 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 8.5.6.1 master eeprom programming below is an example of a 2 kbits (256 x 8-bit) eeprom in hex format for the ds100br111 device. the first 3 bytes of the eeprom always contain a header common and necessary to control initialization of all devices connected to the same smbus line. there is a crc enable flag to enable or disable crc checking. there is a map bit to flag the presence of an address map that specifies the configuration data start address in the eeprom. if the map bit is not present, the configuration data start address immediately follows the 3-byte base header. a bit to indicate an eeprom size > 256 bytes is necessary to address the eeprom properly. there are 37 bytes of data size for each ds100br111 device. for more details about eeprom programming and master mode, refer to snla228 . figure 8. typical eeprom data set note the maximum eeprom size supported is 8 kbits (1024 x 8 bits). the crc-8 calculation is performed for each device on the first 3 bytes of header information plus the 37 bytes of data for the ds100br111 or 40 bytes in total. the result of this calculation is placed immediately after the ds100br111 data in the eeprom which ends with "5454". the crc-8 in the ds100br111 uses a polynomial = x 8 + x 2 + x + 1. there are two pins that provide unique functions in smbus master mode: ? done ? readen when the ds100br111 is powered up in smbus master mode, it reads its configuration from the external eeprom when the readen pin goes low. when the ds100br111 is finished reading its configuration from the external eeprom, it drives the done pin low. in applications where there is more than one ds100br111 on the same smbus, bus contention can result if more than one ds100br111 tries to take control of the smbus at the same time. the readen and done pins prevent this bus contention. the system should be designed so that the readen pin from one ds100br111 in the system is driven low on power-up. this ds100br111 will take command of the smbus on power-up and will read its initial configuration from the external eeprom. when the first ds100br111 is finished reading its configuration, it will drive the done pin low. this pin should be copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: ds100br111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 : 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 4 0 7 0 0 2 f e d 4 0 0 2 f e d 4 0 0 2 f c 4 : 1 0 0 0 1 0 0 0 a d 4 0 0 2 f a d 4 0 0 0 0 5 f 5 6 8 0 0 5 f 5 a 8 0 0 5 f 5 a e 9 : 1 0 0 0 2 0 0 0 8 0 0 5 f 5 a 8 0 0 0 0 5 4 5 4 f 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a 8 : 1 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 : 1 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b 0 : 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a 0 : 1 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 : 1 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 : 1 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 : 1 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 : 1 0 0 0 a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 : 1 0 0 0 b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 : 1 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 : 1 0 0 0 d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 : 1 0 0 0 e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 : 1 0 0 0 f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 1 f f crc-8 based on 40 bytes of data in this shaded area insert the crc value here crc polynomial = 0x07 max eeprom burst = 32
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com connected to the readen pin of another ds100br111. when this second ds100br111 senses its readen pin driven low, it will take command of the smbus and read its initial configuration from the external eeprom, after which it will set its done pin low. by connecting the done pin of each ds100br111 to the readen pin of the next ds100br111, each ds100br111 can read its initial configuration from the eeprom without causing bus contention. figure 9. typical multi-device eeprom connection diagram 8.5.6.2 eeprom address mapping a detailed eeprom address mapping for a single device is shown in table 6 . for instances where multiple devices are written to eeprom, the device starting address definitions align starting with byte 0x03. a register map overview for a multi-device eeprom address map is shown in table 7 . 20 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111 outa+ outa- outb+ vdd_sel vin 18 inb+ inb- 17 14 13 16 los readen done sd_th ina+ ina- outb- smbus and control 15 vdd 24 23 22 21 20 19 11 12 8 10 9 7 ad2 ensmb 1 2 5 63 scl ad3 sda 4 vdd tx_dis ad1 ad0 outa+ outa- outb+ vdd_sel vin 18 inb+ inb- 17 14 13 16 los readen done sd_th ina+ ina- outb- smbus and control 15 vdd 24 23 22 21 20 19 11 12 8 10 9 7 ad2 ensmb 1 2 5 63 scl ad3 sda 4 vdd tx_dis ad1 ad0 outa+ outa- outb+ vdd_sel vin 18 inb+ inb- 17 14 13 16 los readen done sd_th ina+ ina- outb- smbus and control 15 vdd 24 23 22 21 20 19 11 12 8 10 9 7 ad2 ensmb 1 2 5 63 scl ad3 sda 4 vdd tx_dis ad1 ad0 sda scl ad0 ad1 ad2 gnd gnd gnd one or both of these lines should float for eeprom larger than 256 bytes. eeprom sda scl from external smbus master 3.3v float float float note: set ad[3:0] of each ds100br111 to unique smbus address. gnd
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 table 6. single device with default value eeprom address byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address map eeprom > 256 device device device device description crc_en reserved present bytes count[3] count[2] count[1] count[0] 0x00 default 0x00 0 0 0 0 0 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved 0x01 default 0x00 0 0 0 0 0 0 0 0 value max eeprom max eeprom max eeprom max eeprom max eeprom max eeprom max eeprom max eeprom description burst size[7] burst size[6] burst size[5] burst size[4] burst size[3] burst size[2] burst size[1] burst size[0] 0x02 default 0x00 0 0 0 0 0 0 0 0 value cont_talk_en_ch cont_talk_en_ch description reserved reserved reserved sel_los reserved reserved a b smbus register 0x03 0x01[7] 0x01[6] 0x01[5] 0x01[4] 0x01[3] 0x01[2] 0x01[1] 0x01[0] default 0x00 0 0 0 0 0 0 0 0 value description ovrd_los los_value pwdn_inputs pwdn_osc reserved esata en cha esata en chb ovrd tx_dis smbus register 0x02[5] 0x02[4] 0x02[3] 0x02[2] 0x02[0] 0x04[7] 0x04[6] 0x04[5] 0x04 default 0x00 0 0 0 0 0 0 0 0 value description tx_dis cha tx_dis chb reserved eq stage 4 chb eq stage 4 cha reserved ovrd idle_th reserved smbus register 0x04[4] 0x04[3] 0x04[2] 0x04[1] 0x04[0] 0x06[4] 0x08[6] 0x08[5] 0x05 default 0x04 0 0 0 0 0 1 0 0 value description ovrd idle reserved ovrd out_mode ovrd dem reserved reserved reserved reserved smbus register 0x08[4] 0x08[3] 0x08[2] 0x08[1] 0x08[0] 0x0b[6] 0x0b[5] 0x0b[4] 0x06 default 0x07 0 0 0 0 0 1 1 1 value description reserved reserved reserved reserved cha_idle_auto cha_idle_sel reserved reserved smbus register 0x0b[3] 0x0b[2] 0x0b[1] 0x0b[0] 0x0e[5] 0x0e[4] 0x0e[3] 0x0e[2] 0x07 default 0x00 0 0 0 0 0 0 0 0 value copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 21 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com table 6. single device with default value (continued) eeprom address byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 description cha_eq[7] cha_eq[6] cha_eq[5] cha_eq[4] cha_eq[3] cha_eq[2] ch0_eq[1] ch0_eq[0] smbus register 0x0f[7] 0x0f[6] 0x0f[5] 0x0f[4] 0x0f[3] 0x0f[2] 0x0f[1] 0x0f[0] 0x08 default 0x2f 0 0 1 0 1 1 1 1 value description cha_sel scp cha_out mode reserved reserved reserved reserved reserved reserved smbus register 0x10[7] 0x10[6] 0x10[5] 0x10[4] 0x10[3] 0x10[2] 0x10[1] 0x10[0] 0x09 default 0xed 1 1 1 0 1 1 0 1 value description cha_dem[2] cha_dem[1] cha_dem[0] reserved cha_idle_tha[1] cha_idle_tha[0] cha_idle_thd[1] cha_idle_thd[0] smbus register 0x11[2] 0x11[1] 0x11[0] 0x12[7] 0x12[3] 0x12[2] 0x12[1] 0x12[0] 0x0a default 0x40 0 1 0 0 0 0 0 0 value description chb_idle_auto chb_idle_sel reserved reserved chb_eq[7] chb_eq[6] chb_eq[5] chb_eq[4] smbus register 0x15[5] 0x15[4] 0x15[3] 0x15[2] 0x16[7] 0x16[6] 0x16[5] 0x16[4] 0x0b default 0x02 0 0 0 0 0 0 1 0 value description chb_eq[3] chb_eq[2] chb_eq[1] chb_eq[0] chb_sel scp chb_out mode reserved reserved smbus register 0x16[3] 0x16[2] 0x16[1] 0x16[0] 0x17[7] 0x17[6] 0x17[5] 0x17[4] 0x0c default 0xfe 1 1 1 1 1 1 1 0 value description reserved reserved reserved reserved chb_dem[2] chb_dem[1] chb_dem[0] reserved smbus register 0x17[3] 0x17[2] 0x17[1] 0x17[0] 0x18[2] 0x18[1] 0x18[0] 0x19[7] 0x0d default 0xd4 1 1 0 1 0 1 0 0 value description chb_idle_tha[1] chb_idle_tha[0] chb_idle_thd[1] chb_idle_thd[0] reserved reserved reserved reserved smbus register 0x19[3] 0x19[2] 0x19[1] 0x19[0] 0x1c[5] 0x1c[4] 0x1c[3] 0x1c[2] 0x0e default 0x00 0 0 0 0 0 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x1d[7] 0x1d[6] 0x1d[5] 0x1d[4] 0x1d[3] 0x1d[2] 0x1d[1] 0x1d[0] 0x0f default 0x2f 0 0 1 0 1 1 1 1 value 22 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 table 6. single device with default value (continued) eeprom address byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x1e[7] 0x1e[6] 0x1e[5] 0x1e[4] 0x1e[3] 0x1e[2] 0x1e[1] 0x1e[0] 0x10 default 0xad 1 0 1 0 1 1 0 1 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x1f[2] 0x1f[1] 0x1f[0] 0x20[7] 0x20[3] 0x20[2] 0x20[1] 0x20[0] 0x11 default 0x40 0 1 0 0 0 0 0 0 value description reserved cha_vod[2] cha_vod[1] cha_vod[0] reserved reserved reserved reserved smbus register 0x23[5] 0x23[4] 0x23[3] 0x23[2] 0x24[7] 0x24[6] 0x24[5] 0x24[4] 0x12 default 0x02 0 0 0 0 0 0 1 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x24[3] 0x24[2] 0x24[1] 0x24[0] 0x25[7] 0x25[6] 0x25[5] 0x25[4] 0x13 default 0xfa 1 1 1 1 1 0 1 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x25[3] 0x25[2] 0x25[1] 0x25[0] 0x26[2] 0x26[1] 0x26[0] 0x27[7] 0x14 default 0xd4 1 1 0 1 0 1 0 0 value description reserved reserved reserved reserved ovrd_fast idle hi_idle_th_cha hi_idle_th_chb fast_idle_cha smbus register 0x27[3] 0x27[2] 0x27[1] 0x27[0] 0x28[6] 0x28[5] 0x28[4] 0x28[3] 0x15 default 0x00 0 0 0 0 0 0 0 0 value description fast_idle_chb reserved reserved reserved reserved reserved reserved reserved smbus register 0x28[2] 0x28[1] 0x28[0] 0x2b[5] 0x2b[4] 0x2b[3] 0x2b[2] 0x2c[7] 0x16 default 0x00 0 0 0 0 0 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x2c[6] 0x2c[5] 0x2c[4] 0x2c[3] 0x2c[2] 0x2c[1] 0x2c[0] 0x2d[7] 0x17 default 0x5f 0 1 0 1 1 1 1 1 value copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 23 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com table 6. single device with default value (continued) eeprom address byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 description reserved reserved chb_vod[2] chb_vod[1] chb_vod[0] reserved reserved reserved smbus register 0x2d[6] 0x2d[5] 0x2d[4] 0x2d[3] 0x2d[2] 0x2d[1] 0x2d[0] 0x2e[2] 0x18 default 0x5a 0 1 0 1 1 0 1 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x2e[1] 0x2e[0] 0x2f[7] 0x2f[3] 0x2f[2] 0x2f[1] 0x2f[0] 0x32[5] 0x19 default 0x80 1 0 0 0 0 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x32[4] 0x32[3] 0x32[2] 0x33[7] 0x33[6] 0x33[5] 0x33[4] 0x33[3] 0x1a default 0x05 0 0 0 0 0 1 0 1 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x33[2] 0x33[1] 0x33[0] 0x34[7] 0x34[6] 0x34[5] 0x34[4] 0x34[3] 0x1b default 0xf5 1 1 1 1 0 1 0 1 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x34[2] 0x34[1] 0x34[0] 0x35[2] 0x35[1] 0x35[0] 0x36[7] 0x36[3] 0x1c default 0xa8 1 0 1 0 1 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x36[2] 0x36[1] 0x36[0] 0x39[5] 0x39[4] 0x39[3] 0x39[2] 0x3a[7] 0x1d default 0x00 0 0 0 0 0 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x3a[6] 0x3a[5] 0x3a[4] 0x3a[3] 0x3a[2] 0x3a[1] 0x3a[0] 0x3b[7] 0x1e default 0x5f 0 1 0 1 1 1 1 1 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x3b[6] 0x3b[5] 0x3b[4] 0x3b[3] 0x3b[2] 0x3b[1] 0x3b[0] 0x3c[2] 0x1f default 0x5a 0 1 0 1 1 0 1 0 value 24 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 table 6. single device with default value (continued) eeprom address byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x3c[1] 0x3c[0] 0x3d[7] 0x3d[3] 0x3d[2] 0x3d[1] 0x3d[0] 0x40[5] 0x20 default 0x80 1 0 0 0 0 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x40[4] 0x40[3] 0x40[2] 0x41[7] 0x41[6] 0x41[5] 0x41[4] 0x41[3] 0x21 default 0x05 0 0 0 0 0 1 0 1 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x41[2] 0x41[1] 0x41[0] 0x42[7] 0x42[6] 0x42[5] 0x42[4] 0x42[3] 0x22 default 0xf5 1 1 1 1 0 1 0 1 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x42[2] 0x42[1] 0x42[0] 0x43[2] 0x43[1] 0x43[0] 0x44[7] 0x44[3] 0x23 default 0xa8 1 0 1 0 1 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x44[2] 0x44[1] 0x44[0] 0x47[3] 0x47[2] 0x47[1] 0x47[0] 0x48[7] 0x24 default 0x00 0 0 0 0 0 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x48[6] 0x4c[7] 0x4c[6] 0x4c[5] 0x4c[4] 0x4c[3] 0x4c[0] 0x59[0] 0x25 default 0x00 0 0 0 0 0 0 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x5a[7] 0x5a[6] 0x5a[5] 0x5a[4] 0x5a[3] 0x5a[2] 0x5a[1] 0x5a[0] 0x26 default 0x54 0 1 0 1 0 1 0 0 value description reserved reserved reserved reserved reserved reserved reserved reserved smbus register 0x5b[7] 0x5b[6] 0x5b[5] 0x5b[4] 0x5b[3] 0x5b[2] 0x5b[1] 0x5b[0] 0x27 default 0x54 0 1 0 1 0 1 0 0 value copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 25 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com table 7. multi-device eeprom address map overview (1) addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 crc en address map eeprom > 256 reserved count[3] count[2] count[1] count[0] bytes header 1 reserved reserved reserved reserved reserved reserved reserved reserved 2 ee burst[7] ee burst[6] ee burst[5] ee burst[4] ee burst[3] ee burst[2] ee burst[1] ee burst[0] device 0 3 crc[7] crc[6] crc[5] crc[4] crc[3] crc[2] crc[1] crc[0] info 4 ee ad0 [7] ee ad0 [6] ee ad0 [5] ee ad0 [4] ee ad0 [3] ee ad0 [2] ee ad0 [1] ee ad0 [0] device 1 5 crc[7] crc[6] crc[5] crc[4] crc[3] crc[2] crc[1] crc[0] info 6 ee ad1 [7] ee ad1 [6] ee ad1 [5] ee ad1 [4] ee ad1 [3] ee ad1 [2] ee ad1 [1] ee ad1 [0] device 2 7 crc[7] crc[6] crc[5] crc[4] crc[3] crc[2] crc[1] crc[0] info 8 ee ad2 [7] ee ad2 [6] ee ad2 [5] ee ad2 [4] ee ad2 [3] ee ad2 [2] ee ad2 [1] ee ad2 [0] device 3 9 crc[7] crc[6] crc[5] crc[4] crc[3] crc[2] crc[1] crc[0] info 10 ee ad3 [7] ee ad3 [6] ee ad3 [5] ee ad3 [4] ee ad3 [3] ee ad3 [2] ee ad3 [1] ee ad3 [0] device 0 11 res res res res res sel_los res res addr 3 device 0 12 ovrd_los los_value pwdn inp pwdn osc res esata cha esata chb ovrd tx_dis addr 4 device 0 46 res res res res res res res res addr 38 device 0 47 res res res res res res res res addr 39 device 1 48 res res res res res sel_los res res addr 3 device 1 49 ovrd_los los_value pwdn inp pwdn osc res esata cha esata chb ovrd tx_dis addr 4 device 1 83 res res res res res res res res addr 38 device 1 84 res res res res res res res res addr 39 device 2 85 res res res res res sel_los res res addr 3 device 2 86 ovrd_los los_value pwdn inp pwdn osc res esata cha esata chb ovrd tx_dis addr 4 (1) ( a) crc en = 1; address map = 1 ( b) eeprom > 256 bytes = 0 ( c) count[3:0] = 0011 ' b ( d) note: multiple ds100br111 devices may point at the same address space if they have identical programming values. 26 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 table 7. multi-device eeprom address map overview (1) (continued) addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device 2 120 res res res res res res res res addr 38 device 2 121 res res res res res res res res addr 39 device 3 122 res res res res res sel_los res res addr 3 device 3 123 ovrd_los los_value pwdn inp pwdn osc res esata cha esata chb ovrd tx_dis addr 4 device 3 157 res res res res res res res res addr 38 device 3 158 res res res res res res res res addr 39 copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 27 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com table 8. multi ds100br111 eeprom data eeprom address eeprom comments address (hex) data 0 00 0x43 crc_en = 0, address map = 1, device count = 3 (devices 0, 1, 2, and 3) 1 01 0x00 2 02 0x08 eeprom burst size 3 03 0x00 crc not used 4 04 0x0b device 0 address location 5 05 0x00 crc not used 6 06 0x30 device 1 address location 7 07 0x00 crc not used 8 08 0x30 device 2 address location 9 09 0x00 crc not used 10 0a 0x0b device 3 address location 11 0b 0x00 begin device 0 and device 3 - address offset 3 12 0c 0x00 13 0d 0x04 14 0e 0x07 15 0f 0x00 16 10 0x2f default eq cha 17 11 0xed 18 12 0x40 19 13 0x02 default eq chb 20 14 0xfe default eq chb 21 15 0xd4 22 16 0x00 23 17 0x2f 24 18 0xad 25 19 0x40 26 1a 0x02 br111 cha vod = 700 mvpp 27 1b 0xfa 28 1c 0xd4 29 1d 0x00 30 1e 0x00 31 1f 0x5f 32 20 0x5a br111 chb vod = 1000 mvpp 33 21 0x80 34 22 0x05 35 23 0xf5 36 24 0xa8 37 25 0x00 38 26 0x5f 39 27 0x5a 40 28 0x80 41 29 0x05 42 2a 0xf5 43 2b 0xa8 44 2c 0x00 45 2d 0x00 46 2e 0x54 28 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 table 8. multi ds100br111 eeprom data (continued) eeprom address eeprom comments address (hex) data 47 2f 0x54 end device 0 and device 3 - address offset 39 48 30 0x00 begin device 1 and device 2 - address offset 3 49 31 0x00 50 32 0x04 51 33 0x07 52 34 0x00 53 35 0x2f default eq cha 54 36 0xed 55 37 0x40 56 38 0x02 default eq chb 57 39 0xfe default eq chb 58 3a 0xd4 59 3b 0x00 60 3c 0x2f 61 3d 0xad 62 3e 0x40 63 3f 0x02 br111 cha vod = 700 mvpp 64 40 0xfa 65 41 0xd4 66 42 0x00 67 43 0x00 68 44 0x5f 69 45 0x5a br111 chb vod = 1000 mvpp 70 46 0x80 71 47 0x05 72 48 0xf5 73 49 0xa8 74 4a 0x00 75 4b 0x5f 76 4c 0x5a 77 4d 0x80 78 4e 0x05 79 4f 0xf5 80 50 0xa8 81 51 0x00 82 52 0x00 83 53 0x54 84 54 0x54 end device 1 and device 2 - address offset 39 copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 29 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com 8.6 register maps table 9. smbus slave mode register map register eeprom address bit field type default description name reg bit 7 reserved r/w set bit to 0 smbus address 6:3 r smbus strap observation [3:0] 0x00 device id 0x00 eeprom reading 1 = eeprom done loading 2 r done 0 = eeprom loading 1:0 reserved rwsc set bits to 0 continuous talk control (output always on) 7:6 idle control [7]: continuous talk enable (channel a) [6]: continuous talk enable (channel b) 5:3 reserved set bits to 0 0x01 control 1 r/w 0x00 yes los monitor selection 2 los select 1 = use los from ch b 0 = use los from ch a 1:0 reserved set bits to 0 7:6 reserved set bits to 0 1 = los pin override enable 5 los override yes 0 = use normal signal detection 1 = normal operation 4 los override value yes 0 = output los 0x02 control 2 r/w 0x00 3 pwdn inputs yes 1 = pwdn 0 = normal operation 2 pwdn oscillator yes 1 reserved set bit to 0 0 reserved yes set bit to 0 0x03 reserved 7:0 reserved r/w 0x00 reserved esata mode [7] channel a (1) 7:6 enable [6] channel b (1) tx_dis override 1 = override use reg 0x04[4:3] 5 enable 0 = normal operation - uses pin tx_dis value 1 = channel a tx disabled 4 channel a 0 = channel a tx enabled tx_dis value 1 = channel b tx disabled 3 channel b 0 = channel b tx enabled 0x04 control 3 r/w 0x00 yes 2 reserved set bit to 0 [1]: channel b - eq stage 4 limiting on/off [0]: channel a - eq stage 4 limiting on/off setting this control bit turns on added voltage gain compared to normal operating range. if the eq stage 4 1:0 bits are set to 1 (on), the eq will act as a limiting control limiting amplifier, resulting in reduction of overall linear gain characteristics. turning these bits on is not recommended for 10g-kr applications. 0x05 reserved 7:0 reserved r/w 0x00 reserved 30 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 register maps (continued) table 9. smbus slave mode register map (continued) register eeprom address bit field type default description name reg bit disable eeprom 7 disable master mode eeprom configuration cfg 6:5 reserved set bits to 0 4 reserved yes set bit to 1 1 = enable smbus slave mode register slave control 0x06 register r/w 0x10 0 = disable smbus slave mode register control 3 register enable control note: in order to change vod, dem, and eq of the channels in slave mode, this bit must be set to 1. 2:1 reserved set bits to 0 0 reserved set bit to 0 7 reserved set bit to 0 1 = self clearing reset for smbus registers 6 reset registers (register settings return to default values) digital reset 0x07 r/w 0x01 and control reset smbus 1 = self clearing reset to smbus master state 5 master machine 4:0 reserved set bits to 0 0001'b 7 reserved set bit to 0 1 = override by channel - see reg 0x13 and override idle 6 yes 0x19 threshold 0 = sd_th pin control 5 reserved yes set bit to 0 1 = force idle by channel - see reg 0x0e 4 override idle yes and 0x15 0 = normal operation set bit to 0 note: for all applications operating > 8gbps, 3 reserved 0x08 pin override r/w 0x00 users must set this bit to 1 and enable all channels manually. 1 = enable output mode control for individual yes outputs. see register locations 0x10[6] and override output 0x17[6]. 2 mode 0 = disable - outputs are kept in the normal mode of operation allowing vod and de adjustments. 1 override dem yes override de-emphasis (ignore rate) 0 reserved yes set bit to 0 0x09-0x0a reserved 7:0 reserved r/w 0x00 reserved 7 reserved reserved 0x0b reserved r/w 0x70 6:0 reserved yes reserved ch a 0x0c analog 7:0 reserved r/w 0x00 set bits to 0x00 override 1 ch a 0x0d 7:0 reserved r/w 0x00 set bits to 0x00. reserved copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 31 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com register maps (continued) table 9. smbus slave mode register map (continued) register eeprom address bit field type default description name reg bit 7:6 reserved set bits to 0 1 = allow idle select control in bit 4 0 = automatic idle detect 5 idle auto yes (must set 0x08[4] = 1 to override pin-select control) ch a 0x0e r/w 0x00 1 = output is muted (electrical idle) idle control 0 = output is on 4 idle select yes (must set 0x08[4] = 1 to override pin-select control) 3:2 reserved yes set bits to 0 1:0 reserved set bits to 0 ch a eq boost default to 24 db 0x0f 7:0 boost [7:0] r/w 0x2f yes eq setting see table 3 for information 1 = short circuit protection on 7 sel_scp yes 0 = short circuit protection off 1 = normal operation ch a 6 output mode yes 0x10 r/w 0xed 0 = 10g-kr operation control 1 5:3 reserved yes set bits to 101'b 2:0 reserved yes set bits to 101'b 7:5 reserved r set bits to 100'b 4:3 reserved set bits to 0 de-emphasis 000'b = -0.0 db 001'b = -1.5 db ch a 0x11 0x82 010'b = -3.5 db (default) control 2 r/w 2:0 dem [2:0] yes 011'b = -6.0 db 100'b = -8.0 db 101'b = -9.0 db 110'b = -10.5 db 111'b = -12.0 db 7 reserved yes set bit to 0 6:4 reserved set bits to 0 assert thresholds use only if register 0x08 [6] = 1 idle assert 00'b = 180 mvpp (default) 3:2 yes threshold[1:0] 01'b = 160 mvpp ch a 10'b = 210 mvpp 0x12 idle r/w 0x00 11'b = 190 mvpp threshold de-assert thresholds use only if register 0x08 [6] = 1 idle de-assert 00'b = 110 mvpp (default) 1:0 yes threshold[1:0] 01'b = 100 mvpp 10'b = 150 mvpp 11'b = 130 mvpp ch b 0x13 analog 7:0 reserved r/w 0x00 set bits to 0x00 override 1 ch b 0x14 7:0 reserved r/w 0x00 set bits to 0x00 reserved 32 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 register maps (continued) table 9. smbus slave mode register map (continued) register eeprom address bit field type default description name reg bit 7:6 reserved set bits to 0 1 = allow idle select control in bit 4 0 = automatic idle detect 5 idle auto yes (must set 0x08[4] = 1 to override pin-select control) ch b 0x15 r/w 0x00 1 = output is muted (electrical idle) idle control 0 = output is on 4 idle select yes (must set 0x08[4] = 1 to override pin-select control) 3:2 reserved yes set bits to 0 1:0 reserved set bits to 0 ch b eq boost default to 24 db 0x16 7:0 boost [7:0] r/w 0x2f yes eq setting see table 3 for information 1 = short circuit protection on 7 sel_scp yes 0 = short circuit protection off 1 = normal operation ch b 6 output mode yes 0x17 r/w 0xed 0 = 10g-kr operation control 1 5:3 reserved yes set bits to 101'b 2:0 reserved yes set bits to 101'b 7:5 reserved r set bits to 100'b 4:3 reserved set bits to 0 de-emphasis (default = -3.5 db) 000'b = -0.0 db 001'b = -1.5 db ch b 0x18 0x82 010'b = -3.5 db control 2 r/w 2:0 dem [2:0] yes 011'b = -6.0 db 100'b = -8.0 db 101'b = -9.0 db 110'b = -10.5 db 111'b = -12.0 db 7 reserved yes set bit to 0 6:4 reserved set bits to 0 assert thresholds use only if register 0x08 [6] = 1 idle assert 00'b = 180 mvpp (default) 3:2 yes threshold[1:0] 01'b = 160 mvpp ch b 10'b = 210 mvpp 0x19 idle r/w 0x00 11'b = 190 mvpp threshold de-assert thresholds use only if register 0x08 [6] = 1 idle de-assert 00'b = 110 mvpp (default) 1:0 yes threshold[1:0] 01'b = 100 mvpp 10'b = 150 mvpp 11'b = 130 mvpp 0x1a-0x1b reserved 7:0 reserved r/w 0x00 reserved 7:6 reserved reserved 0x1c reserved 5:2 reserved r/w 0x00 yes reserved 1:0 reserved reserved 0x1d reserved 7:0 reserved r/w 0x2f yes reserved 0x1e reserved 7:0 reserved r/w 0xad yes reserved 7:3 reserved reserved 0x1f reserved r/w 0x02 2:0 reserved yes reserved copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 33 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com register maps (continued) table 9. smbus slave mode register map (continued) register eeprom address bit field type default description name reg bit 7 reserved yes reserved 0x20 reserved 6:4 reserved r/w 0x00 reserved 3:0 reserved yes reserved 0x21-0x22 reserved 7:0 reserved r/w 0x00 reserved 7:6 reserved set bits to 0 5 reserved yes set bit to 0 vod controls for ch a 000'b = 700 mvpp (default) 001'b = 800 mvpp ch a vod 0x23 r/w 0x00 010'b = 900 mvpp control 4:2 vod_cha[2:0] yes 011'b = 1000 mvpp 100'b = 1100 mvpp 101'b = 1200 mvpp 110'b = 1300 mvpp 1:0 reserved set bits to 0 0x24 reserved 7:0 reserved r/w 0x2f yes reserved 0x25 reserved 7:0 reserved r/w 0xad yes reserved 7:3 reserved reserved 0x26 reserved r/w 0x02 2:0 reserved yes reserved 7 reserved yes reserved 0x27 reserved 6:4 reserved r/w 0x00 reserved 3:0 reserved yes reserved 7 reserved set bit to 0 1 = enable fast idle control in reg 0x28[3:2] 6 override fast idle yes 0 = disable fast idle control in reg 0x28[3:2]. enable high sd thresholds (slow idle) 5:4 en_hi_idle_th[1:0] yes [5]: ch a 0x28 idle control r/w 0x00 [4]: ch b enable fast idle 3:2 en_fast_idle[1:0] yes [3]: ch a [2]: ch b 1:0 reserved yes set bits to 0 0x29-0x2a reserved 7:0 reserved r/w 0x00 reserved 7:6 reserved reserved 0x2b reserved 5:2 reserved r/w 0x00 yes reserved 1:0 reserved reserved 0x2c reserved 7:0 reserved r/w 0x2f yes reserved 7:5 reserved yes set bits to 101'b vod controls for ch b 000'b = 700 mvpp 001'b = 800 mvpp ch b vod 010'b = 900 mvpp 0x2d 4:2 vod_chb[2:0] r/w 0xad yes control 011'b = 1000 mvpp (default) 100'b = 1100 mvpp 101'b = 1200 mvpp 110'b = 1300 mvpp 1:0 reserved yes set bits to 01'b 7:3 reserved reserved 0x2e reserved r/w 0x02 2:0 reserved yes reserved 34 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 register maps (continued) table 9. smbus slave mode register map (continued) register eeprom address bit field type default description name reg bit 7 reserved yes reserved 0x2f reserved 6:4 reserved r/w 0x00 reserved 3:0 reserved yes reserved 0x30-0x31 reserved 7:0 reserved r/w 0x00 reserved 7:6 reserved reserved 0x32 reserved 5:2 reserved r/w 0x00 yes reserved 1:0 reserved reserved 0x33 reserved 7:0 reserved r/w 0x2f yes reserved 0x34 reserved 7:0 reserved r/w 0xad yes reserved 7:3 reserved reserved 0x35 reserved r/w 0x02 2:0 reserved yes reserved 7 reserved yes reserved 0x36 reserved 6:4 reserved r/w 0x00 reserved 3:0 reserved yes reserved 0x37-0x38 reserved 7:0 reserved r/w 0x00 reserved 7:6 reserved reserved 0x39 reserved 5:2 reserved r/w 0x00 yes reserved 1:0 reserved reserved 0x3a reserved 7:0 reserved r/w 0x2f yes reserved 0x3b reserved 7:0 reserved r/w 0xad yes reserved 7:3 reserved reserved 0x3c reserved r/w 0x02 2:0 reserved yes reserved 7 reserved yes reserved 0x3d reserved 6:4 reserved r/w 0x00 reserved 3:0 reserved yes reserved 0x3e-0x3f reserved 7:0 reserved r/w 0x00 reserved 7:6 reserved reserved 0x40 reserved 5:2 reserved r/w 0x00 yes reserved 1:0 reserved reserved 0x41 reserved 7:0 reserved r/w 0x2f yes reserved 0x42 reserved 7:0 reserved r/w 0xad yes reserved 7:3 reserved reserved 0x43 reserved r/w 0x02 2:0 reserved yes reserved 7 reserved yes reserved 0x44 reserved 6:4 reserved r/w 0x00 reserved 3:0 reserved yes reserved 0x45 reserved 7:0 reserved r/w 0x00 reserved 0x46 reserved 7:0 reserved r/w 0x38 reserved 7:4 reserved reserved 0x47 reserved r/w 0x00 3:0 reserved yes reserved 7:6 reserved yes reserved 0x48 reserved r/w 0x05 5:0 reserved reserved 0x49-0x4b reserved 7:0 reserved r/w 0x00 reserved copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 35 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com register maps (continued) table 9. smbus slave mode register map (continued) register eeprom address bit field type default description name reg bit 7:3 reserved yes reserved 0x4c reserved 2:1 reserved r/w 0x00 reserved 0 reserved yes reserved 0x4d-0x50 reserved 7:0 reserved r/w 0x00 reserved 7:5 version 011'b device 0x51 r 0x67 information 4:0 device id 0 0111'b 0x52-0x55 reserved 7:0 reserved r/w 0x00 reserved 0x56 reserved 7:0 reserved r/w 0x02 reserved 0x57 reserved 7:0 reserved r/w 0x14 reserved 0x58 reserved 7:0 reserved r/w 0x21 reserved 7:1 reserved reserved 0x59 reserved r/w 0x00 0 reserved yes reserved 0x5a reserved 7:0 reserved r/w 0x54 yes reserved 0x5b reserved 7:0 reserved r/w 0x54 yes reserved 0x5c-0x61 reserved 7:0 reserved r/w 0x00 reserved 36 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information 9.1.1 signal integrity in 10g-kr applications when configured in "kr mode", using either the vod_sel and mode pin setting or smbus register control, the ds100br111 is designed to operate transparently within a kr backplane channel environment. installing a ds100br111 repeater within the kr backplane channel splits the total channel attenuation into two parts. in other words, operating in "kr mode" implies that signals will pass through the repeater with a linearized output. ideally the repeater can be placed near the middle of the channel, maximizing the signal-to-noise ratio across the bidirectional interface. in order to maximize the 10g-kr solution space, the 802.3ap specification calls for an optimization of the tx partner signal conditioning coefficients based on feedback from the kr rx asic endpoint. this link optimization sequence is commonly referred to as "link training" and is performed at speed (10.3125 gbps). setting the ds100br111 active ctle to compensate for the channel loss from each of the kr transmitters will reduce the transmit and receive equalization settings required on the kr physical layer devices. this central location keeps a larger signal-to-noise ratio at all points in the channel, extending the available solution space and increasing the overall margin of almost any channel. suggested initial settings for the ds100br111 are given in table 10 and table 11 . further adjustments to eqx, demx, and vodx settings may optimize signal margin on the link for different system applications. table 10. suggested 10g-kr initial device settings in pin mode (1) channel settings pin mode eqx[1:0] 0, 0 vod_sel 1 demx 0 (1) for 10g-kr mode with slow idle-to-active response, the mode pin should be left floating. table 11. suggested 10g-kr initial device settings in smbus modes channel settings smbus modes eqx 0x00 vodx 100'b demx 000'b the smbus slave mode code example in table 12 may be used to program the ds100br111 with the recommended device settings. table 12. smbus 10g-kr example sequence register write value comments 0x06 0x18 set smbus slave mode register enable. 0x08 0x04 enable output mode control for individual channel outputs. 0x0f 0x00 set cha eq to 0x00. set cha output mode to linear (10g-kr mode). 0x10 0xad if link-training is not required, set reg 0x10 to 0xed. 0x11 0x00 set cha dem to 000'b. 0x16 0x00 set chb eq to 0x00. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 37 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com table 12. smbus 10g-kr example sequence (continued) register write value comments set chb output mode to linear (10g-kr mode). 0x17 0xad if link-training is not required, set reg 0x18 to 0xed. 0x18 0x00 set chb dem to 000'b. 0x23 0x10 set cha vod to 100'b. leave idle control at default levels. 0x28 0x00 for sas/sata applications, set reg 0x28 to 0x4c. 0x2d 0xb1 set chb vod to 100'b. 9.1.2 oob (out-of-band) functionality in sas/sata applications for sas/sata systems, a low speed oob (out-of-band) communication sequence is used to detect and communicate device capabilities between host asic and link partners. these oob signals, including comwake, cominit, comreset, and comsas, are a series of burst, idle, and negation times transmitted and detected across the sas/sata link. these bursts occur at a rapid rate, with the comwake signal having the most stringent requirement of 106.6 ns active followed by 106.6 ns idle. normally, if the device is set in 10g- kr mode (mode pin floating), the device goes idle-to-active in approximately 150 ns. if the device is set to sas mode (mode pin tied via 1 k to vdd (2.5 v mode) or vin (3.3 v mode)), the device goes idle-to-active in approximately 3 to 4 ns. this fast idle-to-active time is critical to pass oob signaling, and when operating in pin mode, the mode pin should be tied high. if operating in smbus slave mode, the user can set reg 0x28 to 0x4c for this faster idle-to-active response. 9.2 typical application the ds100br111 works to extend the reach possible by using active equalization on the channel, boosting attenuated signals so that they can be more easily recovered at the rx endpoint. the capability of the repeater can be explored across a range of data rates and asic-to-link-partner signaling, as shown in the following test setup connections. figure 10 through figure 12 represent typical generic application scenarios for the ds100br111. figure 10. test setup connections diagram pre-channel only figure 11. test setup connections diagram pre-channel and post-channel, no tx source de-emphasis figure 12. test setup connections diagram pre-channel and post-channel, -6 db tx source de-emphasis 38 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111 pattern generator v od = 1.0 vp-p, de = -6 db prbs-11 scope bw = 60 ghz ds100br111 tl1 lossy channel in out tl2 lossy channel pattern generator v od = 1.0 vp-p, de = 0 db prbs-11 scope bw = 60 ghz ds100br111 tl1 lossy channel in out tl2 lossy channel pattern generator v od = 1.0 vp-p, de = 0 db prbs-11 scope bw = 60 ghz ds100br111 in out tl lossy channel
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 typical application (continued) 9.2.1 design requirements as with any high speed design, there are many factors that influence the overall performance. below are a list of critical areas for consideration during design. ? use 100 impedance traces. length matching on the p and n traces should be done on the single-ended segments of the differential pair. ? use uniform trace width and trace spacing for differential pairs. ? place ac-coupling capacitors near to the receiver end of each channel segment to minimize reflections. ? the maximum body size for ac-coupling capacitors is 0402. ? back-drill connector vias and signal vias to minimize stub length. ? use reference plane vias to ensure a low inductance path for the return current. 9.2.2 detailed design procedure the ds100br111 is designed to be placed at an offset location with respect to the overall channel attenuation. in order to optimize performance, the repeater requires optimization to extend the reach of the cable or trace length while also recovering a solid eye opening. to optimize the repeater in a 10g-kr environment, the settings mentioned in table 10 (for pin mode) and table 11 (for smbus modes) are recommended as a default starting point. for a generic 10gbe application where link training is not required, the following settings in table 13 and table 14 may be referenced as an initial starting point: table 13. suggested generic 10gbe initial device settings in pin mode (1) channel settings pin mode eqx[1:0] 0, 0 vod_sel 0 demx 0 (1) for 10gbe applications, the mode pin should be tied high. table 14. suggested generic 10gbe initial device settings in smbus modes channel settings smbus modes eqx 0x00 vodx 000'b demx 000'b examples of the repeater performance are illustrated in the performance curves in the next section. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 39 product folder links: ds100br111
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com 9.2.3 application performance plots the lab setups referenced in figure 10 to figure 12 were used to collect typical performance data on fr4 and cable media. for all measurements, mode pin = float. 9.2.3.1 equalization results (pre-channel only) no repeater used ds100br111 settings: eqa = 0x01, dema = 000 ' b, vod = 000 ' b figure 13. tl = 5 inch 4 ? mil fr4 trace, figure 14. tl = 5 inch 4 ? mil fr4 trace, no repeater, 8 gbps ds100br111 cha, 10.3125 gbps no repeater used ds100br111 settings: eqa = 0x02, dema =000 ' b, voda = 000 ' b figure 15. tl = 10 inch 4 ? mil fr4 trace, figure 16. tl= 10 inch 4 ? mil fr4 trace, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps no repeater used ds100br111 settings: eqa = 0x03, dema = 000 ' b, vod = 000 ' b figure 17. tl = 15 inch 4 ? mil fr4 trace, figure 18. tl = 15 inch 4 ? mil fr4 trace, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps 40 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111 cml serializer data throughput (170 mv/div) time (16.16 ps/div) cml serializer data throughput (140 mv/div) time (16.16 ps/div) cml serializer data throughput (194 mv/div) time (16.16 ps/div) cml serializer data throughput (140 mv/div) time (16.16 ps/div) cml serializer data throughput (202 mv/div) time (16.16 ps/div) cml serializer data throughput (138 mv/div) time (16.16 ps/div)
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 no repeater used ds100br111 settings: eqa = 0x07, dema = 000 ' b, vod = 000 ' b figure 19. tl = 20 inch 4 ? mil fr4 trace, figure 20. tl = 20 inch 4 ? mil fr4 trace, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps no repeater used ds100br111 settings: eqa = 0x0f, dema = 000 ' b, vod = 000 ' b figure 21. tl = 30 inch 4 ? mil fr4 trace, figure 22. tl = 30 inch 4 ? mil fr4 trace, no repeater used, 10.3125 gbps ds100br111 cha, 10.3125 gbps no repeater used ds100br111 settings: eqa = 0x1f, dema = 000 ' b, vod = 000 ' b figure 23. tl = 35 inch 4 ? mil fr4 trace, figure 24. tl = 35 inch 4 ? mil fr4 trace, no repeater used, 10.3125 gbps ds100br111 cha, 10.3125 gbps copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 41 product folder links: ds100br111 cml serializer data throughput (138 mv/div) time (16.16 ps/div) cml serializer data throughput (162 mv/div) time (16.16 ps/div) cml serializer data throughput (162 mv/div) time (16.16 ps/div) cml serializer data throughput (168 mv/div) time (16.16 ps/div) cml serializer data throughput (132 mv/div) time (16.16 ps/div) time (16.16 ps/div) cml serializer data throughput (178 mv/div)
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com no repeater used ds100br111 settings: eqa = 0x03, dema = 000 ' b, voda = 000 ' b figure 25. tl = 3-meter 30-awg 100 twin-axial cable, figure 26. tl = 3-meter 30-awg 100 twin-axial cable, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps no repeater used ds100br111 settings: eqa = 0x0f, dema = 000 ' b, voda = 011 ' b figure 27. tl = 7-meter 30-awg 100 twin-axial cable, figure 28. tl = 7-meter 30-awg 100 twin-axial cable, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps no repeater used ds100br111 settings: eqa = 0x2f, dema = 000 ' b, voda = 000 ' b figure 29. tl = 10-meter 30-awg 100 twin-axial cable, figure 30. tl = 10-meter 30-awg 100 twin-axial cable, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps 42 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111 cml serializer data throughput (114 mv/div) time (16.16 ps/div) cml serializer data throughput (132 mv/div) time (16.16 ps/div) cml serializer data throughput (184 mv/div) time (16.16 ps/div) cml serializer data throughput (184 mv/div) time (16.16 ps/div) cml serializer data throughput (184 mv/div) time (16.16 ps/div) cml serializer data throughput (132 mv/div) time (16.16 ps/div)
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 9.2.3.2 equalization and de-emphasis results (pre-channel and post-channel, no tx source de-emphasis) no repeater used ds100br111 settings: eqa = 0x0b, dema = 010 ' b, vod = 101 ' b figure 31. tl1 = 15 inch 4 ? mil fr4 trace, figure 32. tl1 = 15 inch 4 ? mil fr4 trace, tl2 = 10 inch 4 ? mil fr4 trace, tl2 = 10 inch 4 ? mil fr4 trace, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 43 product folder links: ds100br111 cml serializer data throughput (162 mv/div) time (16.16 ps/div) cml serializer data throughput (132 mv/div) time (16.16 ps/div)
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com 9.2.3.3 equalization and de-emphasis results (pre-channel and post-channel, -6 db tx source de-emphasis) no repeater used ds100br111 settings: eqa = 0x00, dema = 000 ' b, vod = 011 ' b figure 33. tl1 = 15 inch 4 ? mil fr4 trace, figure 34. tl1 = 15 inch 4 ? mil fr4 trace, tl2 = 10 inch 4 ? mil fr4 trace, tl2 = 10 inch 4 ? mil fr4 trace, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps no repeater used ds100br111 settings: eqa = 0x03, dema = 010 ' b, vod = 101 ' b figure 35. tl1 = 30 inch 4 ? mil fr4 trace, figure 36. tl1 = 30 inch 4 ? mil fr4 trace, tl2 = 10 inch 4 ? mil fr4 trace, tl2 = 10 inch 4 ? mil fr4 trace, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps no repeater used ds100br111 settings: eqa = 0x03, dema = 100 ' b, vod = 101 ' b figure 37. tl1 = 40 inch 4 ? mil fr4 trace, figure 38. tl1 = 40 inch 4 ? mil fr4 trace, tl2 = 10 inch 4 ? mil fr4 trace, tl2 = 10 inch 4 ? mil fr4 trace, no repeater, 10.3125 gbps ds100br111 cha, 10.3125 gbps 44 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111 cml serializer data throughput (80 mv/div) time (16.16 ps/div) cml serializer data throughput (130 mv/div) time (16.16 ps/div) cml serializer data throughput (88 mv/div) time (16.16 ps/div) cml serializer data throughput (118 mv/div) time (16.16 ps/div) cml serializer data throughput (72 mv/div) time (16.16 ps/div) cml serializer data throughput (130 mv/div) time (16.16 ps/div)
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 10 power supply recommendations the ds100br111 has an optional internal voltage regulator to provide the 2.5 v supply to the device. in 3.3 v mode, the vin pin = 3.3 v is used to supply power to the device and the vdd pins should be left open. the internal regulator will provide the 2.5 v to the vdd pins of the device and a 0.1 f cap is needed at each of the two vdd pins for power supply de-coupling (total capacitance should be 0.2 f). the vdd_sel pin must be tied to gnd to enable the internal regulator. in 2.5 v mode, the vin pin should be left open and 2.5 v supply must be applied to the vdd pins. the vdd_sel pin must be left open (no connect) to disable the internal regulator. the ds100br111 can be configured for 2.5 v operation or 3.3 v operation. the lists below outline required connections for each supply selection. ? 3.3 v mode of operation ? tie vdd_sel = gnd. ? feed 3.3 v supply into vin pin. local 10 f and 1 f decoupling at vin is recommended. ? see information on vdd bypass in power supply bypass . ? sda and scl pins should connect pull-up resistor to vin. ? any 4-level input which requires a connection to "logic 1" should use a 1 k resistor to vin. ? 2.5 v mode of operation ? vdd_sel = float ? vin = float ? feed 2.5 v supply into vdd pins. local 10 f and 1 f decoupling at vin is recommended. ? see information on vdd bypass in power supply bypass . ? sda and scl pins connect pull-up resistor to vdd for 2.5 v or 3.3 v microcontroller smbus io. ? any 4-level input which requires a connection to "logic 1" should use a 1 k resistor to vdd. note the dap (bottom solder pad) is the gnd connection. figure 39. 3.3 v or 2.5 v supply connection diagram copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 45 product folder links: ds100br111 vdd_sel vin vdd vdd 3.3 v 0.1 f 0.1 f internal voltage regulator enable 2.5 v vdd_sel vin vdd vdd internal voltage regulator disable place 0.1 f capacitors close to vdd pins total capacitance should be 7 0.2 f 1 f 10 f 2.5 v 1 f 10 f 0.1 f 0.1 f place 0.1 f capacitors close to vdd pins open open capacitors can be either tantalum or an ultra-low esr ceramic. 3.3 v mode 2.5 v mode capacitors can be either tantalum or an ultra-low esr ceramic.
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com 10.1 power supply bypass two approaches are recommended to ensure that the ds100br111 is provided with an adequate power supply bypass. first, the supply (vdd) and ground (gnd) pins should be connected to power planes routed on adjacent layers of the printed circuit board. second, careful attention to supply bypassing through the proper use of bypass capacitors is required. a 0.1 f bypass capacitor should be connected to each v dd pin such that the capacitor is placed as close as possible to the device. small body size capacitors (such as 0402) reduce the capacitors' parasitic inductance and also help in placement close to the vdd pin. if possible, the layer thickness of the dielectric should be minimized so that the vdd and gnd planes create a low inductance supply with distributed capacitance. 11 layout 11.1 layout guidelines the differential inputs and outputs are designed with 100 differential terminations. therefore, they should be connected to interconnects with controlled differential impedance of approximately 85-110 . it is preferable to route differential lines primarily on one layer of the board, particularly for the input traces. the use of vias should be avoided if possible. if vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. whenever differential vias are used, the layout must also provide for a low inductance path for the return currents as well. route the differential signals away from other signals and noise sources on the printed circuit board. to minimize the effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair spacing and trace width. see an-1187 ? leadless leadframe package (llp) application report ? (literature number snoa401 ) for additional information on qfn (wqfn) packages. the ds100br111 pinout promotes easy high speed routing and layout. to optimize ds100br111 performance, refer to the following guidelines: 1. place local vin and vdd capacitors as close as possible to the device supply pins. often the best location is directly under the ds100br111 pins to reduce the inductance path to the capacitor. in addition, bypass capacitors may share a via with the dap gnd to minimize ground loop inductance. 2. differential pairs going into or out of the ds100br111 should have adequate pair-to-pair spacing to minimize crosstalk. 3. use return current via connections to link reference planes locally. this ensures a low inductance return current path when the differential signal changes layers. 4. optimize the via structure to minimize trace impedance mismatch. 5. place gnd vias around the dap perimeter to ensure optimal electrical and thermal performance. a 2x2 or 3x3 array of gnd vias for the dap is recommended. 6. use small body size ac coupling capacitors when possible ? 0402 or smaller size is preferred. the ac coupling capacitors should be placed closer to the rx on the channel. 46 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338f ? january 2011 ? revised november 2014 11.2 layout example in most cases, ds100br111 layouts will fit neatly into a 1-lane application. the example layout in figure 40 shows the ds100br111 channels in a typical 1-lane bidirectional layout. figure 40. ds100br111 example layout copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 47 product folder links: ds100br111 v dd 1 23456 22 21 20 19 24 23 9 10 11 12 gnd bottom of pkg (top layer) 8 7 18 17 16 15 14 13 1 2 1 2 1 2 1 2 1 2 1 2 v in 5 55 7 7 5 55 7 7 > 25 via to gnd layer via to gnd layer via to vin layer via to bottom layer pad on bottom layer pad on bottom layer via to gnd layer for return current path uniform trace width and spacing differential vias
ds100br111 snls338f ? january 2011 ? revised november 2014 www.ti.com 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation, see the following: ? absolute maximum ratings for soldering ( snoa549 ). ? leadless leadframe package (llp) application report , an-1187 ( snoa401 ) ? semiconductor and ic package thermal metrics ( spra953 ). 12.2 trademarks all trademarks are the property of their respective owners. 12.3 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.4 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 48 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: ds100br111
package option addendum www.ti.com 18-apr-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ds100br111sq/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 85 br111 ds100br111sqe/nopb active wqfn rtw 24 250 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 85 br111 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 18-apr-2014 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ds100br111sq/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 ds100br111sqe/nopb wqfn rtw 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 package materials information www.ti.com 18-apr-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ds100br111sq/nopb wqfn rtw 24 1000 213.0 191.0 55.0 ds100br111sqe/nopb wqfn rtw 24 250 213.0 191.0 55.0 package materials information www.ti.com 18-apr-2014 pack materials-page 2
mechanical da t a r tw0024a www .ti.com s q a 2 4 a ( r e v b )
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